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| author | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
| commit | 835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch) | |
| tree | 4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/simple_gemac/flow_ctrl_rx.v | |
| parent | f1838b9284a124fcfb5996eaf1647a69b4473278 (diff) | |
| parent | 067491b58676cbdaa754334949a8ffc2daf32979 (diff) | |
| download | uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.gz uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.bz2 uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.zip | |
Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts:
.gitignore
Diffstat (limited to 'fpga/usrp2/simple_gemac/flow_ctrl_rx.v')
| -rw-r--r-- | fpga/usrp2/simple_gemac/flow_ctrl_rx.v | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_rx.v b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v new file mode 100644 index 000000000..d09bf377f --- /dev/null +++ b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v @@ -0,0 +1,61 @@ +
+// RX side of flow control -- when we are running out of RX space, send a PAUSE
+
+module flow_ctrl_rx
+ (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh,
+ input rx_clk, input rx_reset, input [15:0] rx_fifo_space,
+ input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req
+ );
+
+ // ******************************************************************************
+ // Force our TX to send a PAUSE frame because our RX is nearly full
+ // ******************************************************************************
+
+ // RX Clock Domain
+ reg xon, xoff;
+ reg [21:0] countdown;
+
+ wire [15:0] pause_low_thresh = pause_thresh;
+ wire [15:0] pause_hi_thresh = 16'hFFFF;
+ wire [21:0] pq_reduced = {pause_time,6'd0} - 1700;
+
+ always @(posedge rx_clk)
+ if(rx_reset)
+ xoff <= 0;
+ else
+ xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh));
+
+ always @(posedge rx_clk)
+ if(rx_reset)
+ xon <= 0;
+ else
+ xon <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh));
+
+ always @(posedge rx_clk)
+ if(rx_reset)
+ countdown <= 0;
+ else if(xoff)
+ countdown <= pq_reduced;
+ else if(xon)
+ countdown <= 0;
+ else if(countdown != 0)
+ countdown <= countdown - 1;
+
+ // Cross clock domains
+ wire xon_tx, xoff_tx;
+ oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx));
+ oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx));
+
+ always @(posedge tx_clk)
+ if(xoff_tx)
+ pause_time_req <= pause_time;
+ else if(xon_tx)
+ pause_time_req <= 0;
+
+ always @(posedge tx_clk)
+ if(tx_reset)
+ pause_req <= 0;
+ else
+ pause_req <= xon_tx | xoff_tx;
+
+endmodule // flow_ctrl_rx
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