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authorJosh Blum <josh@joshknows.com>2011-11-07 17:09:07 -0800
committerJosh Blum <josh@joshknows.com>2011-11-07 17:09:07 -0800
commit11f1390bbde65c60f45962acb128cac1ce21e474 (patch)
tree372f2e426781de9885889bec6aa98697006268ec /fpga/usrp2/sdr_lib/small_hb_int.v
parent902818f50bbd486138a7d4cd2ce9ba3661f4a732 (diff)
parentbcb80c5cf9a2117f9d6d22b8e793ea2ecb68ed1f (diff)
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Merge branch 'fpga_master' into uhd_next
Diffstat (limited to 'fpga/usrp2/sdr_lib/small_hb_int.v')
-rw-r--r--fpga/usrp2/sdr_lib/small_hb_int.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga/usrp2/sdr_lib/small_hb_int.v b/fpga/usrp2/sdr_lib/small_hb_int.v
index 387f9e1cb..b69c45413 100644
--- a/fpga/usrp2/sdr_lib/small_hb_int.v
+++ b/fpga/usrp2/sdr_lib/small_hb_int.v
@@ -73,8 +73,8 @@ module small_hb_int
final_round (.clk(clk),.in(accum),.out(accum_rnd));
wire [WIDTH-1:0] clipped;
- clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH))
- final_clip (.clk(clk),.in(accum_rnd),.out(clipped));
+ clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip
+ (.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped));
reg [WIDTH-1:0] saved, saved_d3;
always @(posedge clk)