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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp2/sdr_lib/rx_dcoffset_tb.v')
-rw-r--r--fpga/usrp2/sdr_lib/rx_dcoffset_tb.v25
1 files changed, 25 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
new file mode 100644
index 000000000..a8b4ec20f
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
@@ -0,0 +1,25 @@
+
+`timescale 1ns/1ns
+module rx_dcoffset_tb();
+
+ reg clk, rst;
+
+ initial rst = 1;
+ initial #1000 rst = 0;
+ initial clk = 0;
+ always #5 clk = ~clk;
+
+ initial $dumpfile("rx_dcoffset_tb.vcd");
+ initial $dumpvars(0,rx_dcoffset_tb);
+
+ reg [13:0] adc_in = 7;
+ wire [13:0] adc_out;
+
+ always @(posedge clk)
+ $display("%d\t%d",adc_in,adc_out);
+
+ rx_dcoffset #(.WIDTH(14),.ADDR(0))
+ rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
+ .adc_in(adc_in),.adc_out(adc_out));
+
+endmodule // longfifo_tb