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| author | Josh Blum <josh@joshknows.com> | 2013-09-04 14:35:22 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-09-04 14:35:22 -0700 |
| commit | 91b5557527896998b395f4683914c4bfecad1f8e (patch) | |
| tree | 1817747cc4c63a049bc95b4d2c5cb8b173d7f6ef /fpga/usrp2/sdr_lib/dspengine_8to16.v | |
| parent | 8814558fcad1e1425d929035a651ab51aad05994 (diff) | |
| parent | 8c1b63e1949134ec476b5b43e1caca42ffe017d5 (diff) | |
| download | uhd-91b5557527896998b395f4683914c4bfecad1f8e.tar.gz uhd-91b5557527896998b395f4683914c4bfecad1f8e.tar.bz2 uhd-91b5557527896998b395f4683914c4bfecad1f8e.zip | |
Merge branch 'master_converter_work'
Diffstat (limited to 'fpga/usrp2/sdr_lib/dspengine_8to16.v')
| -rw-r--r-- | fpga/usrp2/sdr_lib/dspengine_8to16.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp2/sdr_lib/dspengine_8to16.v b/fpga/usrp2/sdr_lib/dspengine_8to16.v index 85187d78d..64246ac13 100644 --- a/fpga/usrp2/sdr_lib/dspengine_8to16.v +++ b/fpga/usrp2/sdr_lib/dspengine_8to16.v @@ -1,5 +1,5 @@ -// Copyright 2012 Ettus Research LLC +// Copyright 2012-2013 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -75,13 +75,13 @@ module dspengine_8to16 wire [15:0] data_in_lenx2 = {data_in_len[14:0], 1'b0} - is_odd; reg [7:0] i8_0, q8_0; - wire [7:0] i8_1 = access_dat_i[31:24]; - wire [7:0] q8_1 = access_dat_i[23:16]; + wire [7:0] i8_1 = access_dat_i[15:8]; + wire [7:0] q8_1 = access_dat_i[7:0]; reg skip; always @(posedge clk) - { i8_0, q8_0 } <= access_dat_i[15:0]; + { i8_0, q8_0 } <= access_dat_i[31:16]; always @(posedge clk) if(reset | clear) |