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authorJosh Blum <josh@joshknows.com>2013-09-04 14:35:22 -0700
committerJosh Blum <josh@joshknows.com>2013-09-04 14:35:22 -0700
commit91b5557527896998b395f4683914c4bfecad1f8e (patch)
tree1817747cc4c63a049bc95b4d2c5cb8b173d7f6ef /fpga/usrp2/sdr_lib/dspengine_16to8.v
parent8814558fcad1e1425d929035a651ab51aad05994 (diff)
parent8c1b63e1949134ec476b5b43e1caca42ffe017d5 (diff)
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Merge branch 'master_converter_work'
Diffstat (limited to 'fpga/usrp2/sdr_lib/dspengine_16to8.v')
-rw-r--r--fpga/usrp2/sdr_lib/dspengine_16to8.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/fpga/usrp2/sdr_lib/dspengine_16to8.v b/fpga/usrp2/sdr_lib/dspengine_16to8.v
index 448c57d35..1d6746dd1 100644
--- a/fpga/usrp2/sdr_lib/dspengine_16to8.v
+++ b/fpga/usrp2/sdr_lib/dspengine_16to8.v
@@ -1,5 +1,5 @@
-// Copyright 2011-2012 Ettus Research LLC
+// Copyright 2011-2013 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -181,8 +181,8 @@ module dspengine_16to8
assign access_dat_o = (dsp_state == DSP_WRITE_HEADER) ? { 4'h1, new_header } :
(dsp_state == DSP_WRITE_TRAILER) ? { 4'h2, new_trailer } :
- (last_o&~even_o) ? {4'h0, 16'd0, i8, q8 } :
- {4'h0, i8, q8, i8_reg, q8_reg };
+ (last_o&~even_o) ? {4'h0, i8, q8, 16'd0 } :
+ {4'h0, i8_reg, q8_reg, i8, q8 };
assign access_adr = (stb_write|(dsp_state == DSP_WRITE_HEADER)|(dsp_state == DSP_WRITE_TRAILER)) ? write_adr : read_adr;