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authorJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
committerJosh Blum <josh@joshknows.com>2010-04-16 09:42:46 +0000
commit835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch)
tree4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/sdr_lib/add2_reg.v
parentf1838b9284a124fcfb5996eaf1647a69b4473278 (diff)
parent067491b58676cbdaa754334949a8ffc2daf32979 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts: .gitignore
Diffstat (limited to 'fpga/usrp2/sdr_lib/add2_reg.v')
-rw-r--r--fpga/usrp2/sdr_lib/add2_reg.v17
1 files changed, 17 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/add2_reg.v b/fpga/usrp2/sdr_lib/add2_reg.v
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+
+module add2_reg
+ #(parameter WIDTH=16)
+ (input clk,
+ input [WIDTH-1:0] in1,
+ input [WIDTH-1:0] in2,
+ output reg [WIDTH-1:0] sum);
+
+ wire [WIDTH-1:0] sum_int;
+
+ add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int));
+
+ always @(posedge clk)
+ sum <= sum_int;
+
+endmodule // add2_reg
+