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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
| commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
| tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/sdr_lib/add2_reg.v | |
| parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
| parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
| download | uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.gz uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.bz2 uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.zip | |
Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/sdr_lib/add2_reg.v')
| -rw-r--r-- | fpga/usrp2/sdr_lib/add2_reg.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/fpga/usrp2/sdr_lib/add2_reg.v b/fpga/usrp2/sdr_lib/add2_reg.v new file mode 100644 index 000000000..456cf315b --- /dev/null +++ b/fpga/usrp2/sdr_lib/add2_reg.v @@ -0,0 +1,17 @@ + +module add2_reg + #(parameter WIDTH=16) + (input clk, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + sum <= sum_int; + +endmodule // add2_reg + |