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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp2/sdr_lib/add2_and_clip.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp2/sdr_lib/add2_and_clip.v')
| -rw-r--r-- | fpga/usrp2/sdr_lib/add2_and_clip.v | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/fpga/usrp2/sdr_lib/add2_and_clip.v b/fpga/usrp2/sdr_lib/add2_and_clip.v deleted file mode 100644 index 663f5d004..000000000 --- a/fpga/usrp2/sdr_lib/add2_and_clip.v +++ /dev/null @@ -1,12 +0,0 @@ - -module add2_and_clip - #(parameter WIDTH=16) - (input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output [WIDTH-1:0] sum); - - wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2}; - clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip - (.in(sum_int),.out(sum)); - -endmodule // add2_and_clip |