moved usrp1 and usrp2 fpga dirs into fpga subdirectory

1 files changed, 11 insertions, 0 deletions

diff --git a/fpga/usrp2/sdr_lib/add2.v b/fpga/usrp2/sdr_lib/add2.v
new file mode 100644
index 000000000..13fff803e
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/add2.v
@@ -0,0 +1,11 @@
+
+module add2
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1];  // Note -- will have some bias
+   
+endmodule // add2