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| author | Matt Ettus <matt@ettus.com> | 2010-03-24 16:36:16 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-24 16:36:16 -0700 |
| commit | fc32fa87bc579dfcb04a7a404e6785ac0dc86949 (patch) | |
| tree | 0fc6085d23bf4ddfe425e4f04a4eee2a2a2f2b5d /fpga/usrp2/opencores | |
| parent | 8bf96b82706d8a61cb4140dca713479a13ff4f55 (diff) | |
| download | uhd-fc32fa87bc579dfcb04a7a404e6785ac0dc86949.tar.gz uhd-fc32fa87bc579dfcb04a7a404e6785ac0dc86949.tar.bz2 uhd-fc32fa87bc579dfcb04a7a404e6785ac0dc86949.zip | |
Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround
Diffstat (limited to 'fpga/usrp2/opencores')
0 files changed, 0 insertions, 0 deletions