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authorJosh Blum <josh@joshknows.com>2012-07-18 13:45:42 -0700
committerJosh Blum <josh@joshknows.com>2012-07-18 13:45:42 -0700
commitbd807be75170ef3b97264c3ac6b2693b6c6b2e13 (patch)
treeabe3d553f496ad8e0c23f016e4ae4d6c6e185a38 /fpga/usrp2/opencores/zpu/wishbone
parent9ecbfeb8ee52b6a59b8757cb259b325cebd05199 (diff)
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u1plus: added sr misc hook for clock sync
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