Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

11 files changed, 2195 insertions, 0 deletions

diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
new file mode 100644
index 000000000..a889c3f22
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
new file mode 100644
index 000000000..92755d5f3
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps b/fpga/usrp2/opencores/spi_boot/doc/src/architecture.eps
new file mode 100644
index 000000000..3e70efdb1
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--- /dev/null
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diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/initialization.fig b/fpga/usrp2/opencores/spi_boot/doc/src/initialization.fig
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diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig b/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
new file mode 100644
index 000000000..3d1724050
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
@@ -0,0 +1,119 @@
+#FIG 3.2
+Landscape
+Center
+Metric
+A4      
+65.00
+Single
+-2
+1200 2
+6 2700 4725 4860 5445
+6 2970 4860 4590 5265
+4 1 0 50 0 16 10 0.0000 4 120 435 3780 5017 CMD18\001
+4 1 0 50 0 16 10 0.0000 4 120 1560 3780 5242 READ_MULTIPLE_BLOCKS\001
+-6
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 2745 4770 4815 4770 4815 5400 2745 5400 2745 4770
+-6
+6 3015 2745 4545 3465
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+	 3060 2790 4500 2790 4500 3420 3060 3420 3060 2790
+4 1 0 50 0 16 10 0.0000 4 120 705 3780 3150 Wait for start\001
+-6
+6 3015 3735 4545 4455
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 3780 3780 4500 4050 3780 4410 3060 4050 3780 3780
+4 1 0 50 0 16 10 0.0000 4 135 615 3780 4132 mode = 1?\001
+-6
+6 3015 5715 4545 6435
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 3060 5760 4500 5760 4500 6390 3060 6390 3060 5760
+4 1 0 50 0 16 10 0.0000 4 120 645 3780 6120 Read block\001
+-6
+6 3015 6705 4545 7425
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 3780 6750 4500 7020 3780 7380 3060 7020 3780 6750
+4 1 0 50 0 16 10 0.0000 4 120 675 3780 7102 ???_done?\001
+-6
+6 2835 7695 4725 8415
+6 3105 7830 4455 8235
+4 1 0 50 0 16 10 0.0000 4 120 435 3780 7987 CMD12\001
+4 1 0 50 0 16 10 0.0000 4 120 1290 3780 8212 STOP_TRANSMISSION\001
+-6
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 2880 7740 4680 7740 4680 8370 2880 8370 2880 7740
+-6
+6 5895 4725 7425 5445
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+	 5940 4770 7380 4770 7380 5400 5940 5400 5940 4770
+4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001
+-6
+6 5895 5715 7425 6435
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760
+4 1 0 50 0 16 10 0.0000 4 135 855 6660 6112 cfg_init_n low?\001
+-6
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+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750
+4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001
+-6
+6 5895 7695 7425 8415
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740
+4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001
+-6
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 3420 3780 3780
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 4410 3780 4770
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 5400 3780 5760
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 7380 3780 7740
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4
+	1 1 1.00 45.00 90.00
+	 4545 7020 5130 7020 5130 5535 3780 5535
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 6
+	1 1 1.00 45.00 90.00
+	 3780 8370 3780 8640 2520 8640 2520 2520 3780 2520 3780 2790
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 4680 3555 3780 3555
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 3
+	1 1 1.00 45.00 90.00
+	 4500 4050 6660 4050 6660 4770
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4
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+	 7380 6030 7920 6030 7920 4050 6660 4050
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4
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+	 7380 8010 7920 8010 7920 6525 6660 6525
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 5
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+	 6660 8370 6660 8640 5310 8640 5310 4545 3780 4545
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
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+	1 1 1.00 45.00 90.00
+	 6660 7380 6660 7740
+4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001
+4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001
+4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001
+4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001
+4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001
+4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001