Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 102 insertions, 0 deletions

diff --git a/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h b/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h
new file mode 100644
index 000000000..7f7cfc417
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h
@@ -0,0 +1,102 @@
+/*
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Include file for OpenCores I2C Master core                 ////
+////                                                             ////
+////  File    : oc_i2c_master.h                                  ////
+////  Function: c-include file                                   ////
+////                                                             ////
+////  Authors: Richard Herveille (richard@asics.ws)              ////
+////           Filip Miletic                                     ////
+////                                                             ////
+////           www.opencores.org                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    Filip Miletic                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+*/
+
+/*
+ * Definitions for the Opencores i2c master core
+ */
+
+/* --- Definitions for i2c master's registers --- */
+	
+/* ----- Read-write access                                            */
+
+#define OC_I2C_PRER_LO 0x00     /* Low byte clock prescaler register  */	
+#define OC_I2C_PRER_HI 0x01     /* High byte clock prescaler register */	
+#define OC_I2C_CTR     0x02     /* Control register                   */	
+										
+/* ----- Write-only registers                                         */
+										
+#define OC_I2C_TXR     0x03     /* Transmit byte register             */	
+#define OC_I2C_CR      0x04     /* Command register                   */	
+	
+/* ----- Read-only registers                                          */
+										
+#define OC_I2C_RXR     0x03     /* Receive byte register              */
+#define OC_I2C_SR      0x04     /* Status register                    */
+	
+/* ----- Bits definition                                              */
+	
+/* ----- Control register                                             */
+	
+#define OC_I2C_EN (1<<7)        /* Core enable bit:                   */
+                                /*      1 - core is enabled           */
+                                /*      0 - core is disabled          */
+#define OC_I2C_IEN (1<<6)       /* Interrupt enable bit               */
+                                /*      1 - Interrupt enabled         */
+                                /*      0 - Interrupt disabled        */
+                                /* Other bits in CR are reserved      */
+
+/* ----- Command register bits                                        */
+ 
+#define OC_I2C_STA (1<<7)       /* Generate (repeated) start condition*/
+#define OC_I2C_STO (1<<6)       /* Generate stop condition            */
+#define OC_I2C_RD  (1<<5)       /* Read from slave                    */
+#define OC_I2C_WR  (1<<4)       /* Write to slave                     */
+#define OC_I2C_ACK (1<<3)       /* Acknowledge from slave             */
+                                /*      1 - ACK                       */
+                                /*      0 - NACK                      */
+#define OC_I2C_IACK (1<<0)      /* Interrupt acknowledge              */
+
+/* ----- Status register bits                                         */
+
+#define OC_I2C_RXACK (1<<7)     /* ACK received from slave            */
+                                /*      1 - ACK                       */
+                                /*      0 - NACK                      */
+#define OC_I2C_BUSY  (1<<6)     /* Busy bit                           */
+#define OC_I2C_TIP   (1<<1)     /* Transfer in progress               */
+#define OC_I2C_IF    (1<<0)     /* Interrupt flag                     */
+
+/* bit testing and setting macros                                     */
+
+#define OC_ISSET(reg,bitmask)       ((reg)&(bitmask))
+#define OC_ISCLEAR(reg,bitmask)     (!(OC_ISSET(reg,bitmask)))
+#define OC_BITSET(reg,bitmask)      ((reg)|(bitmask))
+#define OC_BITCLEAR(reg,bitmask)    ((reg)|(~(bitmask)))
+#define OC_BITTOGGLE(reg,bitmask)   ((reg)^(bitmask))
+#define OC_REGMOVE(reg,value)       ((reg)=(value))
\ No newline at end of file