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| author | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
| commit | a9319441d688620e18d5621cc59b98769e670468 (patch) | |
| tree | 834918c47d69808ca163746788c7a1e0a14462aa /fpga/usrp2/opencores/i2c/rtl/verilog | |
| parent | 2f9b6d5530df140a5a03120adc98a5ad32a69cc4 (diff) | |
| parent | 1c1d967ec73906d50ee6e7257a4153db4ab9c507 (diff) | |
| download | uhd-a9319441d688620e18d5621cc59b98769e670468.tar.gz uhd-a9319441d688620e18d5621cc59b98769e670468.tar.bz2 uhd-a9319441d688620e18d5621cc59b98769e670468.zip | |
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Diffstat (limited to 'fpga/usrp2/opencores/i2c/rtl/verilog')
4 files changed, 0 insertions, 8 deletions
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Entries b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Entries deleted file mode 100644 index 441bd81af..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,6 +0,0 @@ -/i2c_master_bit_ctrl.v/1.12/Mon Sep 4 09:08:13 2006// -/i2c_master_byte_ctrl.v/1.7/Wed Feb 18 11:40:46 2004// -/i2c_master_defines.v/1.3/Mon Nov 5 11:59:25 2001// -/i2c_master_top.v/1.11/Sun Feb 27 09:26:24 2005// -/timescale.v/1.1/Mon Sep 24 12:21:50 2001// -D diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Repository b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Repository deleted file mode 100644 index 49cc6cce0..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/rtl/verilog diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Root b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Template b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Template +++ /dev/null |