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| author | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
| commit | edcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch) | |
| tree | 1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/opencores/i2c/bench/verilog | |
| parent | a89d684ba2b81c6e18d348965dffb919edb56fea (diff) | |
| parent | 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff) | |
| download | uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.gz uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.bz2 uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.zip | |
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts:
fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/opencores/i2c/bench/verilog')
4 files changed, 0 insertions, 7 deletions
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Entries b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Entries deleted file mode 100644 index 2dd779100..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Entries +++ /dev/null @@ -1,5 +0,0 @@ -/i2c_slave_model.v/1.7/Mon Sep 4 09:08:51 2006// -/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004// -/tst_bench_top.v/1.8/Mon Sep 4 09:08:51 2006// -/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004// -D diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Repository b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Repository deleted file mode 100644 index b37c379e9..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -i2c/bench/verilog diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Root b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Template b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Template +++ /dev/null |