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authorJosh Blum <josh@joshknows.com>2010-06-15 18:24:33 -0700
committerJosh Blum <josh@joshknows.com>2010-06-15 18:24:33 -0700
commitedcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch)
tree1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/opencores/aemb/sim
parenta89d684ba2b81c6e18d348965dffb919edb56fea (diff)
parent9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff)
downloaduhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.gz
uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.bz2
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Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts: fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/opencores/aemb/sim')
-rw-r--r--fpga/usrp2/opencores/aemb/sim/CVS/Entries3
-rw-r--r--fpga/usrp2/opencores/aemb/sim/CVS/Repository1
-rw-r--r--fpga/usrp2/opencores/aemb/sim/CVS/Root1
-rw-r--r--fpga/usrp2/opencores/aemb/sim/CVS/Template0
-rw-r--r--fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries3
-rw-r--r--fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository1
-rw-r--r--fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root1
-rw-r--r--fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template0
8 files changed, 0 insertions, 10 deletions
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Entries b/fpga/usrp2/opencores/aemb/sim/CVS/Entries
deleted file mode 100644
index bf457ae67..000000000
--- a/fpga/usrp2/opencores/aemb/sim/CVS/Entries
+++ /dev/null
@@ -1,3 +0,0 @@
-D/verilog////
-/cversim/1.5/Tue Jan 15 18:38:57 2008//
-/iversim/1.5/Tue Jan 15 18:38:57 2008//
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Repository b/fpga/usrp2/opencores/aemb/sim/CVS/Repository
deleted file mode 100644
index c6bd1aa80..000000000
--- a/fpga/usrp2/opencores/aemb/sim/CVS/Repository
+++ /dev/null
@@ -1 +0,0 @@
-aemb/sim
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Root b/fpga/usrp2/opencores/aemb/sim/CVS/Root
deleted file mode 100644
index 44b2aa23b..000000000
--- a/fpga/usrp2/opencores/aemb/sim/CVS/Root
+++ /dev/null
@@ -1 +0,0 @@
-:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Template b/fpga/usrp2/opencores/aemb/sim/CVS/Template
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/opencores/aemb/sim/CVS/Template
+++ /dev/null
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries
deleted file mode 100644
index 34e896e80..000000000
--- a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries
+++ /dev/null
@@ -1,3 +0,0 @@
-/aemb2.v/1.3/Tue Jan 15 18:38:57 2008//
-/edk32.v/1.12/Tue Jan 15 18:38:57 2008//
-D
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository
deleted file mode 100644
index ff3eabf2d..000000000
--- a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository
+++ /dev/null
@@ -1 +0,0 @@
-aemb/sim/verilog
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root
deleted file mode 100644
index 44b2aa23b..000000000
--- a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root
+++ /dev/null
@@ -1 +0,0 @@
-:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template
deleted file mode 100644
index e69de29bb..000000000
--- a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template
+++ /dev/null