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| author | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
| commit | 835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch) | |
| tree | 4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/opencores/aemb/sim/cversim | |
| parent | f1838b9284a124fcfb5996eaf1647a69b4473278 (diff) | |
| parent | 067491b58676cbdaa754334949a8ffc2daf32979 (diff) | |
| download | uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.gz uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.bz2 uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.zip | |
Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts:
.gitignore
Diffstat (limited to 'fpga/usrp2/opencores/aemb/sim/cversim')
| -rwxr-xr-x | fpga/usrp2/opencores/aemb/sim/cversim | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp2/opencores/aemb/sim/cversim b/fpga/usrp2/opencores/aemb/sim/cversim new file mode 100755 index 000000000..0dbb7aea1 --- /dev/null +++ b/fpga/usrp2/opencores/aemb/sim/cversim @@ -0,0 +1,22 @@ +#!/bin/sh +# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $ +# $Log: cversim,v $ +# Revision 1.5 2007/12/11 00:44:30 sybreon +# Modified for AEMB2 +# +# Revision 1.4 2007/11/30 17:08:30 sybreon +# Moved simulation kernel into code. +# +# Revision 1.3 2007/11/05 10:59:31 sybreon +# Added random seed for simulation. +# +# Revision 1.2 2007/04/12 20:21:33 sybreon +# Moved testbench into /sim/verilog. +# Simulation cleanups. +# +# Revision 1.1 2007/03/09 17:41:55 sybreon +# initial import +# +RANDOM=$(date +%s) +echo "parameter randseed = $RANDOM;" > random.v +cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v |