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| author | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
| commit | a9319441d688620e18d5621cc59b98769e670468 (patch) | |
| tree | 834918c47d69808ca163746788c7a1e0a14462aa /fpga/usrp2/opencores/aemb/rtl | |
| parent | 2f9b6d5530df140a5a03120adc98a5ad32a69cc4 (diff) | |
| parent | 1c1d967ec73906d50ee6e7257a4153db4ab9c507 (diff) | |
| download | uhd-a9319441d688620e18d5621cc59b98769e670468.tar.gz uhd-a9319441d688620e18d5621cc59b98769e670468.tar.bz2 uhd-a9319441d688620e18d5621cc59b98769e670468.zip | |
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Diffstat (limited to 'fpga/usrp2/opencores/aemb/rtl')
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/CVS/Entries | 1 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/CVS/Repository | 1 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/CVS/Root | 1 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/CVS/Template | 0 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries | 38 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository | 1 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root | 1 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template | 0 | ||||
| -rw-r--r-- | fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v | 9 |
9 files changed, 6 insertions, 46 deletions
diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Entries b/fpga/usrp2/opencores/aemb/rtl/CVS/Entries deleted file mode 100644 index 428c5622d..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/CVS/Entries +++ /dev/null @@ -1 +0,0 @@ -D/verilog//// diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Repository b/fpga/usrp2/opencores/aemb/rtl/CVS/Repository deleted file mode 100644 index e2c1eab77..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/rtl diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Root b/fpga/usrp2/opencores/aemb/rtl/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Template b/fpga/usrp2/opencores/aemb/rtl/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/CVS/Template +++ /dev/null diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries deleted file mode 100644 index f17d70235..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries +++ /dev/null @@ -1,38 +0,0 @@ -/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008// -/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008// -/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008// -/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008// -/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008// -/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008// -/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008// -/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008// -/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008// -/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008// -/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008// -/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008// -/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008// -/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008// -/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008// -/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008// -/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008// -/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008// -/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008// -/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008// -/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009// -/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008// -D diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository deleted file mode 100644 index a9de19556..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository +++ /dev/null @@ -1 +0,0 @@ -aemb/rtl/verilog diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root deleted file mode 100644 index 44b2aa23b..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root +++ /dev/null @@ -1 +0,0 @@ -:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template deleted file mode 100644 index e69de29bb..000000000 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template +++ /dev/null diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v index 9ac45299b..7fe108957 100644 --- a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v +++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v @@ -146,9 +146,12 @@ module aeMB_regf (/*AUTOARG*/ // LUT RAM implementation is smaller and faster. R0 gets written // during reset with 0x00 and doesn't change after. - reg [31:0] mARAM[0:31], - mBRAM[0:31], - mDRAM[0:31]; + //synthesis attribute ram_style of mARAM is distributed + reg [31:0] mARAM[0:31]; + //synthesis attribute ram_style of mBRAM is distributed + reg [31:0] mBRAM[0:31]; + //synthesis attribute ram_style of mDRAM is distributed + reg [31:0] mDRAM[0:31]; wire [31:0] rREGW = mDRAM[rRW]; wire [31:0] rREGD = mDRAM[rRD]; |