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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 15:35:48 -0800 |
| commit | f56c1247cbe7b7e90acee2711b5dda3356b9486a (patch) | |
| tree | 81dadc83537c2c50550cd94e224571e472176c6f /fpga/usrp2/opencores/Makefile.srcs | |
| parent | 9f94ef843ceca63bcb83b2d473cbba709c9110b6 (diff) | |
| parent | eb26e8adb4a5718ee3db3bb7f32c0cd31d060af9 (diff) | |
| download | uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.gz uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.tar.bz2 uhd-f56c1247cbe7b7e90acee2711b5dda3356b9486a.zip | |
Merge branch 'next' of ettus.sourcerepo.com:ettus/uhdpriv into next
Diffstat (limited to 'fpga/usrp2/opencores/Makefile.srcs')
| -rw-r--r-- | fpga/usrp2/opencores/Makefile.srcs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs index 30360a17d..284578b39 100644 --- a/fpga/usrp2/opencores/Makefile.srcs +++ b/fpga/usrp2/opencores/Makefile.srcs @@ -24,5 +24,5 @@ spi/rtl/verilog/spi_clgen.v \ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ spi/rtl/verilog/spi_top.v \ -spi/rtl/verilog/timescale.v \ +spi/rtl/verilog/spi_top16.v \ )) |