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| author | Josh Blum <josh@joshknows.com> | 2010-10-27 11:36:57 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-27 11:36:57 -0700 |
| commit | cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7 (patch) | |
| tree | 92e2c73cd37f4bde6dd6b4a0765e44c9586e7dcd /fpga/usrp2/opencores/Makefile.srcs | |
| parent | 1289d051a1934e48d77be695059b1d23f8668d8a (diff) | |
| parent | 1f77494788fa4fa8450aaf170055553bd0e5fe8e (diff) | |
| download | uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.tar.gz uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.tar.bz2 uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.zip | |
Merge branch 'ue1_rev2' into usrp_e_next
Diffstat (limited to 'fpga/usrp2/opencores/Makefile.srcs')
| -rw-r--r-- | fpga/usrp2/opencores/Makefile.srcs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/fpga/usrp2/opencores/Makefile.srcs b/fpga/usrp2/opencores/Makefile.srcs index 30360a17d..1ccecf337 100644 --- a/fpga/usrp2/opencores/Makefile.srcs +++ b/fpga/usrp2/opencores/Makefile.srcs @@ -23,6 +23,5 @@ i2c/rtl/verilog/timescale.v \ spi/rtl/verilog/spi_clgen.v \ spi/rtl/verilog/spi_defines.v \ spi/rtl/verilog/spi_shift.v \ -spi/rtl/verilog/spi_top.v \ -spi/rtl/verilog/timescale.v \ +spi/rtl/verilog/spi_top16.v \ )) |