Merge branch 'fpga_master'

1 files changed, 59 insertions, 0 deletions

diff --git a/fpga/usrp2/models/IBUFG.v b/fpga/usrp2/models/IBUFG.v
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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG.v,v 1.7 2007/05/23 21:43:34 patrickp Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Input Clock Buffer
+// /___/   /\     Filename : IBUFG.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:24 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    05/23/07 - Changed timescale to 1 ps / 1 ps.
+
+`timescale  1 ps / 1 ps
+
+
+module IBUFG (O, I);
+
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IOSTANDARD = "DEFAULT";
+
+    output O;
+    input  I;
+
+    buf B1 (O, I);
+    
+    initial begin
+	
+        case (CAPACITANCE)
+
+            "LOW", "NORMAL", "DONT_CARE" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFG instance %m is set to %s.  Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
+                          $finish;
+                      end
+
+        endcase
+
+
+	case (IBUF_DELAY_VALUE)
+
+            "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFG instance %m is set to %s.  Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
+                          $finish;
+                      end
+
+        endcase
+
+    end // initial begin
+    
+endmodule