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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp2/models/CY7C1356C/readme.txt | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp2/models/CY7C1356C/readme.txt')
| -rw-r--r-- | fpga/usrp2/models/CY7C1356C/readme.txt | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/fpga/usrp2/models/CY7C1356C/readme.txt b/fpga/usrp2/models/CY7C1356C/readme.txt deleted file mode 100644 index 3578c80dc..000000000 --- a/fpga/usrp2/models/CY7C1356C/readme.txt +++ /dev/null @@ -1,33 +0,0 @@ -***************************
-Cypress Semiconductor
-MPD Applications
-Verilog model for NoBL SRAM CY7C1356
-Created: August 04, 2004
-Rev: 1.0
-***************************
-
-This is the verilog model for the CY7C1356 along with the testbench and test vectors.
-
-Contact support@cypress.com if you have any questions.
-
-This directory has 4 files. including this readme.
-
-1)cy7c1356c.v -> Verilog model for CY7C1356c
-
-2)cy1356.inp -> Test Vector File used for testing the verilog model
-
-3)testbench.v -> Test bench used for testing the verilog model
-
-
-COMPILING METHOD :
-------------------
-
- verilog +define+<speed_bin> <Main File> <Test bench File>
-
- Ex:
- verilog +define+sb133 CY7C1356c.v testbench.v
-
-VERIFIED WITH:
---------------
-
-VERILOG-XL 2.2
\ No newline at end of file |