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author | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-11-23 13:36:42 -0800 |
commit | bb0572a960edf54486a4be746c681adaac0fa398 (patch) | |
tree | 7afb46e99eaf799a478fcde841eb78d7698e9c39 /fpga/usrp2/gpmc/edge_sync.v | |
parent | 8ce75a3ca7a51f4bdee87d78a610a0f2519473ae (diff) | |
download | uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.gz uhd-bb0572a960edf54486a4be746c681adaac0fa398.tar.bz2 uhd-bb0572a960edf54486a4be746c681adaac0fa398.zip |
fpga: performed a forceful checkout of fpga to overwrite with current fpga code
Diffstat (limited to 'fpga/usrp2/gpmc/edge_sync.v')
-rw-r--r-- | fpga/usrp2/gpmc/edge_sync.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/fpga/usrp2/gpmc/edge_sync.v b/fpga/usrp2/gpmc/edge_sync.v new file mode 100644 index 000000000..5d9417c08 --- /dev/null +++ b/fpga/usrp2/gpmc/edge_sync.v @@ -0,0 +1,22 @@ + + +module edge_sync + #(parameter POSEDGE = 1) + (input clk, + input rst, + input sig, + output trig); + + reg [1:0] delay; + + always @(posedge clk) + if(rst) + delay <= 2'b00; + else + delay <= {delay[0],sig}; + + assign trig = POSEDGE ? (delay==2'b01) : (delay==2'b10); + +endmodule // edge_sync + + |