Merge branch 'fpga_master' into uhd_next

2 files changed, 12 insertions, 82 deletions

diff --git a/fpga/usrp2/gpif/gpif.v b/fpga/usrp2/gpif/gpif.v
index 51d6e8ba9..e5b63d5a3 100644
--- a/fpga/usrp2/gpif/gpif.v
+++ b/fpga/usrp2/gpif/gpif.v
@@ -37,10 +37,13 @@ module gpif
     input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
     
     output tx_underrun, output rx_overrun,
-    input [7:0] frames_per_packet, input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl,
+    input [7:0] frames_per_packet,
     output [31:0] debug0, output [31:0] debug1
     );
 
+   assign tx_underrun = 0;
+   assign rx_overrun = 0;
+   
    wire 	  WR = gpif_ctl[0];
    wire 	  RD = gpif_ctl[1];
    wire 	  OE = gpif_ctl[2];
@@ -62,8 +65,8 @@ module gpif
 
    wire [18:0] 	  tx19_data;
    wire 	  tx19_src_rdy, tx19_dst_rdy;
-   wire [35:0] 	  tx36_data, tx_data;
-   wire 	  tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy;
+   wire [35:0] 	  tx36_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy;
 
    wire [18:0] 	  ctrl_data;
    wire 	  ctrl_src_rdy, ctrl_dst_rdy;
@@ -95,13 +98,13 @@ module gpif
    fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
       .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
-      .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy));
+      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
 
    // ////////////////////////////////////////////
    // RX Data Path
 
-   wire [35:0] 	  rx36_data, rx_data;
-   wire 	  rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy;
+   wire [35:0] 	  rx36_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy;
    wire [18:0] 	  rx19_data, splt_data;
    wire 	  rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy;
    wire [18:0] 	  resp_data, resp_int1, resp_int2;
@@ -110,7 +113,7 @@ module gpif
    
    fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
+      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
       .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
 
    fifo36_to_fifo19 #(.LE(1)) f36_to_f19
@@ -166,81 +169,6 @@ module gpif
       .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2),
       .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
         
-   // ////////////////////////////////////////////////////////////////////
-   // Debug support, timed and loopback
-   // RX side muxes test data into the same stream
-   wire [35:0] 	timedrx_data, loopbackrx_data, testrx_data;
-   wire [35:0] 	timedtx_data, loopbacktx_data, testtx_data;
-   wire 	timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy,
-		testrx_src_rdy, testrx_dst_rdy;
-   wire 	timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy,
-		testtx_src_rdy, testtx_dst_rdy;
-   wire 	timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int;
-
-   wire [31:0] 	total, crc_err, seq_err, len_err;
-   wire 	sel_testtx = test_ctrl[0];
-   wire 	sel_loopbacktx = test_ctrl[1];
-   wire 	pkt_src_enable = test_ctrl[2];
-   wire 	pkt_sink_enable = test_ctrl[3];
-   
-   fifo36_mux rx_test_mux_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy),
-      .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy),
-      .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy));
-   
-   fifo36_mux rx_test_mux_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy),
-      .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-   
-   fifo_short #(.WIDTH(36)) loopback_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
-      .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
-      .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
-   
-   // Crossbar used as a demux for switching TX stream to main DSP or to test logic
-   crossbar36 tx_crossbar_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_testtx),
-      .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
-      .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
-      .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) );
-   
-   crossbar36 tx_crossbar_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_loopbacktx),
-      .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy),
-      .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy),
-      .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
-   
-   // Fixed rate TX traffic consumer
-   fifo_pacer tx_pacer
-     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable),
-      .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
-      .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
-      .underrun(tx_underrun), .overrun());
-
-   packet_verifier32 pktver32
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int),
-      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-   // Fixed rate RX traffic generator
-   vita_pkt_gen pktgen
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .len(test_len),
-      .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int));
-
-   fifo_pacer rx_pacer
-     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable),
-      .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
-      .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
-      .underrun(), .overrun(rx_overrun));
-
    // ////////////////////////////////////////////
    //    DEBUG
    
diff --git a/fpga/usrp2/gpif/lint b/fpga/usrp2/gpif/lint
new file mode 100755
index 000000000..4316c89a9
--- /dev/null
+++ b/fpga/usrp2/gpif/lint
@@ -0,0 +1,2 @@
+iverilog -Wall -y . -y ../fifo/ -y ../control_lib/ -y ../models/ -y ../coregen/ -y ../simple_gemac/ -y ../sdr_lib/ -y ../vrt/ gpif.v 2>&1 | grep -v coregen | grep -v models
+