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authorJosh Blum <josh@joshknows.com>2012-10-10 13:24:37 -0700
committerJosh Blum <josh@joshknows.com>2012-10-10 13:24:37 -0700
commitadffee268c57c070ea1ed631a94c24975d0a40ae (patch)
tree49375221347a95fa836096b0ae67fd2e9a543edf /fpga/usrp2/fifo
parent76f4e4d36023555e83cf6a016bbe03c96886f0dc (diff)
parent784edbdf5490d08559b7f2aa24c5bdfac886ccb6 (diff)
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Merge branch 'fpga_master'
Diffstat (limited to 'fpga/usrp2/fifo')
-rw-r--r--fpga/usrp2/fifo/packet_padder36.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/fifo/packet_padder36.v b/fpga/usrp2/fifo/packet_padder36.v
index 7197b5ea5..6ded38781 100644
--- a/fpga/usrp2/fifo/packet_padder36.v
+++ b/fpga/usrp2/fifo/packet_padder36.v
@@ -114,7 +114,7 @@ module packet_padder36
if (src_rdy_i && dst_rdy_o && data_i[32]) begin
vita_hdr <= data_i[31:0];
has_vita_hdr <= 1;
- state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
+ state <= (data_i[15:0] > line_count)? STATE_WRITE_PAD : STATE_WRITE_HDR;
end
else if (force_flush) begin
has_vita_hdr <= 0;