Merge branch 'fpga_next' into uhd_with_fpga_next

1 files changed, 5 insertions, 4 deletions

diff --git a/fpga/usrp2/fifo/valve36.v b/fpga/usrp2/fifo/valve36.v
index b4b23e5a6..d45eee497 100644
--- a/fpga/usrp2/fifo/valve36.v
+++ b/fpga/usrp2/fifo/valve36.v
@@ -7,7 +7,8 @@ module valve36
    output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
    
    reg 		 shutoff_int, active;
-   
+   wire active_next = (src_rdy_i & dst_rdy_o)? ~data_i[33] : active;
+
    assign data_o = data_i;
 
    assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i;
@@ -16,13 +17,13 @@ module valve36
    always @(posedge clk)
      if(reset | clear)
        active <= 0;
-     else if(src_rdy_i & dst_rdy_o)
-       active <= ~data_i[33];
+     else
+       active <= active_next;
    
    always @(posedge clk)
      if(reset | clear)
        shutoff_int <= 0;
-     else if(~active)
+     else if(~active_next)
        shutoff_int <= shutoff;
    
 endmodule // valve36