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author | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
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committer | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
commit | a9319441d688620e18d5621cc59b98769e670468 (patch) | |
tree | 834918c47d69808ca163746788c7a1e0a14462aa /fpga/usrp2/fifo/ll8_shortfifo.v | |
parent | 2f9b6d5530df140a5a03120adc98a5ad32a69cc4 (diff) | |
parent | 1c1d967ec73906d50ee6e7257a4153db4ab9c507 (diff) | |
download | uhd-a9319441d688620e18d5621cc59b98769e670468.tar.gz uhd-a9319441d688620e18d5621cc59b98769e670468.tar.bz2 uhd-a9319441d688620e18d5621cc59b98769e670468.zip |
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Diffstat (limited to 'fpga/usrp2/fifo/ll8_shortfifo.v')
-rw-r--r-- | fpga/usrp2/fifo/ll8_shortfifo.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/fpga/usrp2/fifo/ll8_shortfifo.v b/fpga/usrp2/fifo/ll8_shortfifo.v new file mode 100644 index 000000000..39ada9a4f --- /dev/null +++ b/fpga/usrp2/fifo/ll8_shortfifo.v @@ -0,0 +1,13 @@ + + +module ll8_shortfifo + (input clk, input reset, input clear, + input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o, + output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i); + + fifo_short #(.WIDTH(11)) fifo_short + (.clk(clk), .reset(reset), .clear(clear), + .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + +endmodule // ll8_shortfifo |