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authorJosh Blum <josh@joshknows.com>2010-11-23 09:57:33 -0800
committerJosh Blum <josh@joshknows.com>2010-11-23 09:57:33 -0800
commitd35b7327710f08f96f2cfb93bcc28f14515ea9bb (patch)
tree0cfe31630905570c776a45746fcb3e2011d3dabd /fpga/usrp2/fifo/fifo18_to_fifo36.v
parent6741de7b4545bb33d22cc6508e121023dd1a7a8c (diff)
parent768af46dc01d036999cb60ff16df4215d014c906 (diff)
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Merge branch 'flow_ctrl' into next
Diffstat (limited to 'fpga/usrp2/fifo/fifo18_to_fifo36.v')
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diff --git a/fpga/usrp2/fifo/fifo18_to_fifo36.v b/fpga/usrp2/fifo/fifo18_to_fifo36.v
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+++ b/fpga/usrp2/fifo/fifo18_to_fifo36.v
@@ -0,0 +1,20 @@
+
+// For now just assume FIFO18 is same as FIFO19 without occupancy bit
+
+module fifo18_to_fifo36
+ (input clk, input reset, input clear,
+ input [17:0] f18_datain,
+ input f18_src_rdy_i,
+ output f18_dst_rdy_o,
+
+ output [35:0] f36_dataout,
+ output f36_src_rdy_o,
+ input f36_dst_rdy_i
+ );
+
+ fifo19_to_fifo36 fifo19_to_fifo36
+ (.clk(clk), .reset(reset), .clear(clear),
+ .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o),
+ .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) );
+
+endmodule // fifo18_to_fifo36