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author | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
commit | d35b7327710f08f96f2cfb93bcc28f14515ea9bb (patch) | |
tree | 0cfe31630905570c776a45746fcb3e2011d3dabd /fpga/usrp2/fifo/fifo18_to_fifo36.v | |
parent | 6741de7b4545bb33d22cc6508e121023dd1a7a8c (diff) | |
parent | 768af46dc01d036999cb60ff16df4215d014c906 (diff) | |
download | uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.gz uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.bz2 uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.zip |
Merge branch 'flow_ctrl' into next
Diffstat (limited to 'fpga/usrp2/fifo/fifo18_to_fifo36.v')
-rw-r--r-- | fpga/usrp2/fifo/fifo18_to_fifo36.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/fifo/fifo18_to_fifo36.v b/fpga/usrp2/fifo/fifo18_to_fifo36.v new file mode 100644 index 000000000..25bb215a1 --- /dev/null +++ b/fpga/usrp2/fifo/fifo18_to_fifo36.v @@ -0,0 +1,20 @@ + +// For now just assume FIFO18 is same as FIFO19 without occupancy bit + +module fifo18_to_fifo36 + (input clk, input reset, input clear, + input [17:0] f18_datain, + input f18_src_rdy_i, + output f18_dst_rdy_o, + + output [35:0] f36_dataout, + output f36_src_rdy_o, + input f36_dst_rdy_i + ); + + fifo19_to_fifo36 fifo19_to_fifo36 + (.clk(clk), .reset(reset), .clear(clear), + .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o), + .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) ); + +endmodule // fifo18_to_fifo36 |