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| author | Josh Blum <josh@joshknows.com> | 2010-10-15 11:22:25 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-15 11:22:25 -0700 |
| commit | 52229e99c90966c392f8ec74752912e3f00eec1d (patch) | |
| tree | c72cfdb388745c13c73859cd254bb2ae5d7fb804 /fpga/usrp2/extramfifo/fifo_extram_tb.build | |
| parent | 39ca8e25fc7f9b3170cb517b72640a62b15d253f (diff) | |
| parent | 26b7de0ac0cd64946582b2d52ab0bb3555156039 (diff) | |
| download | uhd-52229e99c90966c392f8ec74752912e3f00eec1d.tar.gz uhd-52229e99c90966c392f8ec74752912e3f00eec1d.tar.bz2 uhd-52229e99c90966c392f8ec74752912e3f00eec1d.zip | |
Merge branch 'flow_ctrl_with_fpga'
Diffstat (limited to 'fpga/usrp2/extramfifo/fifo_extram_tb.build')
| -rwxr-xr-x | fpga/usrp2/extramfifo/fifo_extram_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build new file mode 100755 index 000000000..5607c8691 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v |