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| author | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
| commit | d35b7327710f08f96f2cfb93bcc28f14515ea9bb (patch) | |
| tree | 0cfe31630905570c776a45746fcb3e2011d3dabd /fpga/usrp2/extramfifo/fifo_extram36_tb.build | |
| parent | 6741de7b4545bb33d22cc6508e121023dd1a7a8c (diff) | |
| parent | 768af46dc01d036999cb60ff16df4215d014c906 (diff) | |
| download | uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.gz uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.bz2 uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.zip | |
Merge branch 'flow_ctrl' into next
Diffstat (limited to 'fpga/usrp2/extramfifo/fifo_extram36_tb.build')
| -rwxr-xr-x | fpga/usrp2/extramfifo/fifo_extram36_tb.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.build b/fpga/usrp2/extramfifo/fifo_extram36_tb.build new file mode 100755 index 000000000..ac9369758 --- /dev/null +++ b/fpga/usrp2/extramfifo/fifo_extram36_tb.build @@ -0,0 +1 @@ +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v |