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author | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
commit | d35b7327710f08f96f2cfb93bcc28f14515ea9bb (patch) | |
tree | 0cfe31630905570c776a45746fcb3e2011d3dabd /fpga/usrp2/extramfifo/ext_fifo_tb.prj | |
parent | 6741de7b4545bb33d22cc6508e121023dd1a7a8c (diff) | |
parent | 768af46dc01d036999cb60ff16df4215d014c906 (diff) | |
download | uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.gz uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.bz2 uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.zip |
Merge branch 'flow_ctrl' into next
Diffstat (limited to 'fpga/usrp2/extramfifo/ext_fifo_tb.prj')
-rw-r--r-- | fpga/usrp2/extramfifo/ext_fifo_tb.prj | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.prj b/fpga/usrp2/extramfifo/ext_fifo_tb.prj new file mode 100644 index 000000000..a11a15b2f --- /dev/null +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.prj @@ -0,0 +1,9 @@ +verilog work "./ext_fifo_tb.v" +verilog work "./ext_fifo.v" +verilog work "./nobl_fifo.v" +verilog work "./nobl_if.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v" +verilog work "../models/CY7C1356C/cy1356.v" +verilog work "../models/idt71v65603s150.v" +verilog work "$XILINX/verilog/src/glbl.v" |