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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp2/extramfifo/ext_fifo_tb.cmd | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp2/extramfifo/ext_fifo_tb.cmd')
| -rw-r--r-- | fpga/usrp2/extramfifo/ext_fifo_tb.cmd | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd b/fpga/usrp2/extramfifo/ext_fifo_tb.cmd deleted file mode 100644 index 521f88f21..000000000 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.cmd +++ /dev/null @@ -1,12 +0,0 @@ -/opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v --y . --y ../coregen/ --y ../fifo --y ../models --y /home/ianb/usrp-fpga/usrp2/sdr_lib --y /home/ianb/usrp-fpga/usrp2/control_lib --y /home/ianb/usrp-fpga/usrp2/models --y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/unisims --y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src --y /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/XilinxCoreLib - |