moved usrp1 and usrp2 fpga dirs into fpga subdirectory

4 files changed, 263 insertions, 0 deletions

diff --git a/fpga/usrp2/extram/.gitignore b/fpga/usrp2/extram/.gitignore
new file mode 100644
index 000000000..7fc71ccb6
--- /dev/null
+++ b/fpga/usrp2/extram/.gitignore
@@ -0,0 +1 @@
+/a.out
diff --git a/fpga/usrp2/extram/extram_interface.v b/fpga/usrp2/extram/extram_interface.v
new file mode 100644
index 000000000..7554592ba
--- /dev/null
+++ b/fpga/usrp2/extram/extram_interface.v
@@ -0,0 +1,53 @@
+
+// Temporary buffer pool storage, mostly useful for pre-generated data streams or
+//   for making more space to juggle packets in case of eth frames coming out of order
+
+module extram_interface
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   
+   // Buffer pool interfaces
+   input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
+   input rd_sop_i, input rd_eop_i,
+   output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
+   input wr_ready_i, input wr_full_i,
+   
+   // RAM Interface
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   input RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn );
+
+   // Command format --
+   //    Read/_Write , start address[17:0]
+   wire [18:0] cmd_in;
+   wire        cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
+   wire        empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
+   
+   // Dummy logic
+   assign RAM_OEn = 1;
+   
+   setting_reg #(.my_addr(0)) 
+     sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+		 .in(set_data),.out(cmd_in),.changed(cmd_stb));
+   
+   reg 	  cmd_stb_d1;
+   always @(posedge clk) cmd_stb_d1 <= cmd_stb;
+   assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
+   assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;   
+
+   shortfifo #(.WIDTH(19)) wr_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
+      .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
+
+   shortfifo #(.WIDTH(19)) rd_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
+      .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
+
+endmodule // extram_interface
diff --git a/fpga/usrp2/extram/extram_wb.v b/fpga/usrp2/extram/extram_wb.v
new file mode 100644
index 000000000..c8428783a
--- /dev/null
+++ b/fpga/usrp2/extram/extram_wb.v
@@ -0,0 +1,146 @@
+
+module extram_wb
+  #(parameter PAGE_SIZE = 10,
+    parameter ADDR_WIDTH = 16)
+    (input clk, input rst,
+     input wb_clk, input wb_rst,
+     input cyc_i, input stb_i,
+     input [ADDR_WIDTH-1:0] adr_i,
+     input we_i,
+     input [31:0] dat_i,
+     output reg [31:0] dat_o,
+     output reg ack_o,
+     
+     inout [17:0] RAM_D,
+     output [PAGE_SIZE-2:0] RAM_A,
+     output RAM_CE1n, output RAM_CENn,
+     output RAM_CLK, output RAM_WEn,
+     output RAM_OEn, output RAM_LDn );
+
+   wire     read_acc = stb_i & cyc_i & ~we_i;
+   wire     write_acc = stb_i & cyc_i & we_i;
+   wire     acc = stb_i & cyc_i;
+
+   assign   RAM_CLK = ~wb_clk;   // 50 MHz for now, eventually should be 200 MHz
+   assign   RAM_LDn = 0;        // No burst for now
+   assign   RAM_CENn = 0;       // Use CE1n as our main CE
+
+   reg [PAGE_SIZE-2:1] RAM_addr_reg;
+   always @(posedge wb_clk)
+     if(acc)
+       RAM_addr_reg[PAGE_SIZE-2:1] <= adr_i[PAGE_SIZE-1:2];
+   assign 	       RAM_A[PAGE_SIZE-2:1] = RAM_addr_reg; 
+
+   reg [31:0] 	       ram_out;
+   always @(posedge wb_clk)
+     if(write_acc)
+       ram_out <= dat_i;
+
+   // RAM access state machine
+   localparam RAM_idle = 0;
+   localparam RAM_read_1 = 1;
+   localparam RAM_read_2 = 2;
+   localparam RAM_read_3 = 3;
+   localparam RAM_read_4 = 4;
+   localparam RAM_write_1 = 6;
+   localparam RAM_write_2 = 7;
+   localparam RAM_write_3 = 8;
+   localparam RAM_write_4 = 9;
+
+   reg 	      myOE = 0;
+   reg 	      RAM_OE = 0;
+   reg 	      RAM_WE = 0;
+   reg 	      RAM_EN = 0;
+   reg 	      RAM_A0_reg;
+   reg [3:0]  RAM_state;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  RAM_state <= RAM_idle;
+	  myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+       end
+     else
+       case(RAM_state)
+	 RAM_idle :
+	   if(read_acc & ~ack_o)
+	     begin
+		RAM_state <= RAM_read_1;
+		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0;
+	     end
+	   else if(write_acc & ~ack_o)
+	     begin
+		RAM_state <= RAM_write_1;
+		myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0;
+	     end
+	   else
+	     begin
+		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	     end
+	 RAM_read_1 : 
+	   begin
+	      RAM_state <= RAM_read_2;
+	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 1;
+	   end
+	 RAM_read_2 : 
+	   begin
+	      RAM_state <= RAM_read_3;
+	      myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_read_3 : 
+	   begin
+	      RAM_state <= RAM_read_4;
+	      myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_read_4 :
+	   begin
+	      RAM_state <= RAM_idle;
+	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_write_1 : 
+	   begin
+	      RAM_state <= RAM_write_2;
+	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1;
+	   end
+	 RAM_write_2 : 
+	   begin
+	      RAM_state <= RAM_write_3;
+	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_write_3 : 
+	   begin
+	      RAM_state <= RAM_write_4;
+	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_write_4 : 
+	   begin
+	      RAM_state <= RAM_idle;
+	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 default : RAM_state <= RAM_idle;
+       endcase // case(RAM_state)
+   
+   assign     RAM_A[0] = RAM_A0_reg;
+   assign     RAM_WEn = ~RAM_WE;  // ((RAM_state==RAM_write_1)||(RAM_state==RAM_write_2));
+   assign     RAM_OEn = ~RAM_OE;
+   assign     RAM_CE1n = ~RAM_EN;    // Active low     (RAM_state != RAM_idle);
+   
+   assign     RAM_D[17:16] = 2'bzz;
+   assign     RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) 
+	      : 16'bzzzz_zzzz_zzzz_zzzz;
+
+   always @(posedge wb_clk)
+     if(RAM_state == RAM_read_3)
+       dat_o[15:0] <= RAM_D[15:0];
+     else
+       dat_o[31:16] <= RAM_D[15:0];
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       ack_o <= 0;
+     else if((RAM_state == RAM_write_4)||(RAM_state == RAM_read_4))
+       ack_o <= 1;
+     else
+       ack_o <= 0;
+   
+endmodule // extram_wb
diff --git a/fpga/usrp2/extram/wb_zbt16_b.v b/fpga/usrp2/extram/wb_zbt16_b.v
new file mode 100644
index 000000000..d93e21c99
--- /dev/null
+++ b/fpga/usrp2/extram/wb_zbt16_b.v
@@ -0,0 +1,63 @@
+
+module wb_zbt16_b
+  (input               clk,
+   input               rst,
+   // Wishbone bus A, highest priority, with prefetch
+   input      [19:0]   wb_adr_i,
+   input      [15:0]   wb_dat_i,
+   output reg [15:0]   wb_dat_o,
+   input      [ 1:0]   wb_sel_i,
+   input               wb_cyc_i,
+   input               wb_stb_i,
+   output reg          wb_ack_o,
+   input               wb_we_i,
+   // Memory connection
+   output              sram_clk,
+   output     [18:0]   sram_a,
+   inout      [15:0]   sram_d,
+   output              sram_we,
+   output     [ 1:0]   sram_bw,
+   output              sram_adv,
+   output              sram_ce,
+   output              sram_oe,
+   output              sram_mode,
+   output              sram_zz
+   );
+
+   assign 	       sram_clk = ~clk;
+   //assign 	       sram_oe = 1'b0;
+   assign 	       sram_ce = 1'b0;
+   assign 	       sram_adv = 1'b0;
+   assign 	       sram_mode = 1'b0;
+   assign 	       sram_zz = 1'b0;
+   assign 	       sram_bw = 2'b0;
+   
+   // need to drive wb_dat_o, wb_ack_o,
+   // sram_a, sram_d, sram_we
+   wire 	       myOE;
+   assign 	       sram_d = myOE ? wb_dat_i : 16'bzzzz;
+   assign 	       sram_a = wb_adr_i[19:1];
+
+   reg 		       read_d1, read_d2, read_d3, write_d1, write_d2, write_d3;
+   wire 	       acc = wb_cyc_i & wb_stb_i;
+   wire 	       read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3;
+   wire 	       write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3;
+
+   assign 	       sram_we = ~write_acc;
+   assign 	       sram_oe = ~(read_d2 | read_d3);
+   assign 	       myOE = write_d1 | write_d2;
+   wire 	       latch_now = read_d2;
+
+   always @(posedge clk)
+     if(latch_now)
+       wb_dat_o <= sram_d;
+
+   always @(posedge clk) wb_ack_o <= read_d2 | write_d2;
+   always @(posedge clk) read_d1 <= read_acc;
+   always @(posedge clk) read_d2 <= read_d1;
+   always @(posedge clk) read_d3 <= read_d2;
+   always @(posedge clk) write_d1 <= write_acc;
+   always @(posedge clk) write_d2 <= write_d1;
+   always @(posedge clk) write_d3 <= write_d2;
+endmodule // wb_zbt16_b
+