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| author | Wade Fife <wade.fife@ettus.com> | 2020-08-10 17:24:07 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-08-12 13:56:13 -0500 |
| commit | f48af0a0876c99016eb8cd4558a31106bfc9baa1 (patch) | |
| tree | d17a3e7da096c390ad474c4339d416fba48f0426 /fpga/usrp2/custom | |
| parent | bd851e783658342c313053f6c1e52a68675d59c0 (diff) | |
| download | uhd-f48af0a0876c99016eb8cd4558a31106bfc9baa1.tar.gz uhd-f48af0a0876c99016eb8cd4558a31106bfc9baa1.tar.bz2 uhd-f48af0a0876c99016eb8cd4558a31106bfc9baa1.zip | |
fpga: rfnoc: Fix clock crossing in axis_data_to_chdr
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.
Also cleans up trailing white space.
Diffstat (limited to 'fpga/usrp2/custom')
0 files changed, 0 insertions, 0 deletions