diff options
| author | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-11-23 09:57:33 -0800 |
| commit | d35b7327710f08f96f2cfb93bcc28f14515ea9bb (patch) | |
| tree | 0cfe31630905570c776a45746fcb3e2011d3dabd /fpga/usrp2/coregen/coregen.cgp | |
| parent | 6741de7b4545bb33d22cc6508e121023dd1a7a8c (diff) | |
| parent | 768af46dc01d036999cb60ff16df4215d014c906 (diff) | |
| download | uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.gz uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.tar.bz2 uhd-d35b7327710f08f96f2cfb93bcc28f14515ea9bb.zip | |
Merge branch 'flow_ctrl' into next
Diffstat (limited to 'fpga/usrp2/coregen/coregen.cgp')
| -rw-r--r-- | fpga/usrp2/coregen/coregen.cgp | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp index 810d64dac..4c9201aff 100644 --- a/fpga/usrp2/coregen/coregen.cgp +++ b/fpga/usrp2/coregen/coregen.cgp @@ -1,20 +1,22 @@ -# Date: Thu Sep 3 17:40:48 2009 -SET addpads = False -SET asysymbol = False +# Date: Mon Jul 26 21:55:33 2010 + +SET addpads = false +SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped -SET createndf = False +SET createndf = false SET designentry = Verilog SET device = xc3s2000 SET devicefamily = spartan3 SET flowvendor = Other -SET formalverification = False -SET foundationsym = False +SET formalverification = false +SET foundationsym = false SET implementationfiletype = Ngc SET package = fg456 -SET removerpms = False +SET removerpms = false SET simulationfiles = Behavioral SET speedgrade = -5 -SET verilogsim = True -SET vhdlsim = False -SET workingdirectory = /home/matt/coregen/tmp +SET verilogsim = true +SET vhdlsim = false +SET workingdirectory = /tmp/ +# CRC: 394da717 |