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| author | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-16 09:42:46 +0000 |
| commit | 835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25 (patch) | |
| tree | 4fe48bdaf92311deedfbe1a5e77dd209468a2d7d /fpga/usrp2/coregen/coregen.cgp | |
| parent | f1838b9284a124fcfb5996eaf1647a69b4473278 (diff) | |
| parent | 067491b58676cbdaa754334949a8ffc2daf32979 (diff) | |
| download | uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.gz uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.tar.bz2 uhd-835cb56ef820a69e1e6e0ccde7c5a0e78ca5ad25.zip | |
Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts:
.gitignore
Diffstat (limited to 'fpga/usrp2/coregen/coregen.cgp')
| -rw-r--r-- | fpga/usrp2/coregen/coregen.cgp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp new file mode 100644 index 000000000..810d64dac --- /dev/null +++ b/fpga/usrp2/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Thu Sep 3 17:40:48 2009 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +SET workingdirectory = /home/matt/coregen/tmp + |