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| author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
| commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
| tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/coregen/coregen.cgp | |
| parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
| parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
| download | uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.gz uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.bz2 uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.zip | |
Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/coregen/coregen.cgp')
| -rw-r--r-- | fpga/usrp2/coregen/coregen.cgp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp new file mode 100644 index 000000000..810d64dac --- /dev/null +++ b/fpga/usrp2/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Thu Sep 3 17:40:48 2009 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +SET workingdirectory = /home/matt/coregen/tmp + |