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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
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| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
| commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
| tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp2/coregen/_xmsgs | |
| parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
| download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip | |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp2/coregen/_xmsgs')
| -rw-r--r-- | fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs new file mode 100644 index 000000000..e7bbdb9d5 --- /dev/null +++ b/fpga/usrp2/coregen/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,18 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!-- IMPORTANT: This is an internal file that has been generated --> +<!-- by the Xilinx ISE software. Any direct editing or --> +<!-- changes made to this file may result in unpredictable --> +<!-- behavior or data corruption. It is strongly advised that --> +<!-- users do not edit the contents of this file. --> +<!-- --> +<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. --> + +<messages> +<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file "/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75.v" into library work</arg> +</msg> + +<msg type="info" file="ProjectMgmt" num="1062" ><arg fmt="%s" index="1">Parsing Verilog file "/home/jblum/src/ettus/fpga_b200/usrp2/coregen/pll_100_40_75/example_design/pll_100_40_75_exdes.v" into library work</arg> +</msg> + +</messages> + |