Merge branch 'next' into use_vita_length

3 files changed, 145 insertions, 100 deletions

diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v
index fed2791f9..a161b5e00 100644
--- a/fpga/usrp2/control_lib/atr_controller.v
+++ b/fpga/usrp2/control_lib/atr_controller.v
@@ -7,7 +7,7 @@ module atr_controller
   (input clk_i, input rst_i,
    input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
    input we_i, input stb_i, input cyc_i, output reg ack_o,
-   input run_rx, input run_tx, input [31:0] master_time,
+   input run_rx, input run_tx,
    output [31:0] ctrl_lines);
    
    reg [3:0] state;
diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v
index 3d8b5b1e9..74ce30a54 100644
--- a/fpga/usrp2/control_lib/atr_controller16.v
+++ b/fpga/usrp2/control_lib/atr_controller16.v
@@ -7,7 +7,7 @@ module atr_controller16
   (input clk_i, input rst_i,
    input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
    input we_i, input stb_i, input cyc_i, output reg ack_o,
-   input run_rx, input run_tx, input [31:0] master_time,
+   input run_rx, input run_tx,
    output [31:0] ctrl_lines);
    
    reg [3:0] state;
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v
index 668012504..29d21ab5a 100644
--- a/fpga/usrp2/control_lib/bootram.v
+++ b/fpga/usrp2/control_lib/bootram.v
@@ -6,10 +6,10 @@
 
 module bootram
   (input clk, input reset,
-   input [12:0] if_adr,
+   input [13:0] if_adr,
    output [31:0] if_data,
 
-   input [12:0] dwb_adr_i,
+   input [13:0] dwb_adr_i,
    input [31:0] dwb_dat_i,
    output [31:0] dwb_dat_o,
    input dwb_we_i,
@@ -17,17 +17,23 @@ module bootram
    input dwb_stb_i,
    input [3:0] dwb_sel_i);
 
-   wire [31:0] DOA0, DOA1, DOA2, DOA3;
-   wire [31:0] DOB0, DOB1, DOB2, DOB3;
-   wire        ENB0, ENB1, ENB2, ENB3;
+   wire [31:0] DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7;
+   wire [31:0] DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7;
+   wire        ENB0, ENB1, ENB2, ENB3, ENB4, ENB5, ENB6, ENB7;
    wire [3:0]  WEB;
 
-   reg [1:0]   delayed_if_bank;
+   reg [2:0]   delayed_if_bank;
    always @(posedge clk)
-     delayed_if_bank <= if_adr[12:11];
+     delayed_if_bank <= if_adr[13:11];
    
-   assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0);
-   assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0);
+   assign if_data = delayed_if_bank[2] ?
+                   (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA7 : DOA6) : (delayed_if_bank[0] ? DOA5 : DOA4))
+                 : (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0));
+   
+   
+   assign dwb_dat_o = dwb_adr_i[13] ?
+                     (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB7 : DOB6) : (dwb_adr_i[11] ? DOB5 : DOB4))
+                   : (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0));
 
    always @(posedge clk)
      if(reset)
@@ -35,10 +41,14 @@ module bootram
      else
        dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
    
-   assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00);
-   assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01);
-   assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10);
-   assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11);
+   assign ENB0 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b000);
+   assign ENB1 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b001);
+   assign ENB2 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b010);
+   assign ENB3 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b011);
+   assign ENB4 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b100);
+   assign ENB5 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b101);
+   assign ENB6 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b110);
+   assign ENB7 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b111);
 
    assign WEB = {4{dwb_we_i}} & dwb_sel_i;
    
@@ -161,90 +171,125 @@ module bootram
       .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
       .WEB(WEB)                // Port B 4-bit Write Enable Input
       );   // End of RAMB16BWE_S36_S36_inst instantiation
+      
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM4
+     (.DOA(DOA4),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
 
-endmodule // bootram
+      .DOB(DOB4),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB4),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+      
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM5
+     (.DOA(DOA5),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
 
-/*
-       // The following INIT_xx declarations specify the initial contents of the RAM
-       // Address 0 to 127
-       .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       // Address 128 to 255
-       .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       // Address 256 to 383
-       .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       // Address 384 to 511
-       .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000),
-       // The next set of INITP_xx are for the parity bits
-       // Address 0 to 127
-       .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       // Address 128 to 255
-       .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       // Address 256 to 383
-       .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       // Address 384 to 511
-       .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000),
-       .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000)
-*/
+      .DOB(DOB5),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB5),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+         
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM6
+     (.DOA(DOA6),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB6),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB6),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+      
+   RAMB16BWE_S36_S36 
+     #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup
+       .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup
+       .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL"
+       .SRVAL_A(36'h000000000), // Port       A output value upon SSR    assertion
+       .SRVAL_B(36'h000000000), // Port       B output value upon SSR    assertion
+       .WRITE_MODE_A("WRITE_FIRST"), //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+       .WRITE_MODE_B("WRITE_FIRST")) //       WRITE_FIRST, READ_FIRST    or NO_CHANGE
+   RAM7
+     (.DOA(DOA7),           // Port A 32-bit Data Output
+      .DOPA(),              // Port A 4-bit Parity Output
+      .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input
+      .CLKA(clk),           // Port A 1-bit Clock
+      .DIA(32'd0),          // Port A 32-bit Data Input
+      .DIPA(4'd0),          // Port A 4-bit parity Input
+      .ENA(1'b1),           // Port A 1-bit RAM Enable Input
+      .SSRA(1'b0),          // Port A 1-bit Synchronous Set/Reset Input
+      .WEA(1'b0),           // Port A 4-bit Write Enable Input
+
+      .DOB(DOB7),              // Port B 32-bit Data Output
+      .DOPB(),                 // Port B 4-bit Parity Output
+      .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input
+      .CLKB(clk),              // Port B 1-bit Clock
+      .DIB(dwb_dat_i),         // Port B 32-bit Data Input
+      .DIPB(4'd0),             // Port-B 4-bit parity Input
+      .ENB(ENB7),              // Port B 1-bit RAM Enable Input
+      .SSRB(1'b0),             // Port B 1-bit Synchronous Set/Reset Input
+      .WEB(WEB)                // Port B 4-bit Write Enable Input
+      );   // End of RAMB16BWE_S36_S36_inst instantiation
+
+endmodule // bootram