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| author | Josh Blum <josh@joshknows.com> | 2011-08-15 18:55:57 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-15 18:55:57 -0700 |
| commit | 06dc097530730621515863b40411581e1d3422b7 (patch) | |
| tree | e0fab8d37bc75c16a079647eb2bf58fe072dddfb /fpga/usrp2/control_lib | |
| parent | 26a75aca7c7408dbb9c34d68761b043434e1d13b (diff) | |
| parent | ccafda72b4d1acf820be26e488bbfc530ca31c65 (diff) | |
| download | uhd-06dc097530730621515863b40411581e1d3422b7.tar.gz uhd-06dc097530730621515863b40411581e1d3422b7.tar.bz2 uhd-06dc097530730621515863b40411581e1d3422b7.zip | |
Merge branch 'fpga_patch_release' into patch_releaserelease_003_002_002
Diffstat (limited to 'fpga/usrp2/control_lib')
| -rw-r--r-- | fpga/usrp2/control_lib/bootram.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v index 249a09814..fb7bd46c8 100644 --- a/fpga/usrp2/control_lib/bootram.v +++ b/fpga/usrp2/control_lib/bootram.v @@ -82,7 +82,7 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input + .DIA(32'hffffffff), // Port A 32-bit Data Input .DIPA(4'd0), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input |