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author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/control_lib/wb_ram_block.v | |
parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
download | uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.gz uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.tar.bz2 uhd-3a196c5d614fbec9b1010b3082245614ba5e0dc9.zip |
Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/control_lib/wb_ram_block.v')
-rw-r--r-- | fpga/usrp2/control_lib/wb_ram_block.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/wb_ram_block.v b/fpga/usrp2/control_lib/wb_ram_block.v new file mode 100644 index 000000000..044d34ca4 --- /dev/null +++ b/fpga/usrp2/control_lib/wb_ram_block.v @@ -0,0 +1,36 @@ + + +// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency +// These have to be a multiple of 512 lines (2K) long + +module wb_ram_block + #(parameter AWIDTH=9) + (input clk_i, + input stb_i, + input we_i, + input [AWIDTH-1:0] adr_i, + input [31:0] dat_i, + output reg [31:0] dat_o, + output ack_o); + + reg [31:0] distram [0:1<<(AWIDTH-1)]; + + always @(posedge clk_i) + begin + if(stb_i & we_i) + distram[adr_i] <= dat_i; + dat_o <= distram[adr_i]; + end + + reg stb_d1, ack_d1; + always @(posedge clk_i) + stb_d1 <= stb_i; + + always @(posedge clk_i) + ack_d1 <= ack_o; + + assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1)); +endmodule // wb_ram_block + + + |