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author | Josh Blum <josh@joshknows.com> | 2012-02-17 18:18:26 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2012-02-17 18:18:26 -0800 |
commit | 3ddbcb6078593c39cb0e4bc8f9769f818a61466f (patch) | |
tree | 408e3f6a64e31b7d830b9f884ecebdaf100a5d2d /fpga/usrp2/control_lib/user_settings.v | |
parent | 1fab7e9d477aa98e489400c25a08358952c69c90 (diff) | |
parent | ace4489066d1621a09e70650a00d736f0b03ed8c (diff) | |
download | uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.tar.gz uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.tar.bz2 uhd-3ddbcb6078593c39cb0e4bc8f9769f818a61466f.zip |
Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/control_lib/user_settings.v')
-rw-r--r-- | fpga/usrp2/control_lib/user_settings.v | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/user_settings.v b/fpga/usrp2/control_lib/user_settings.v new file mode 100644 index 000000000..d87f1de21 --- /dev/null +++ b/fpga/usrp2/control_lib/user_settings.v @@ -0,0 +1,63 @@ +// +// Copyright 2012 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// User settings bus +// +// Provides 8-bit address, 32-bit data write only bus for user settings, consumes to addresses in +// normal settings bus. +// +// Write user address to BASE +// Write user data to BASE+1 +// +// The user_set_stb will strobe after data write, must write new address even if same as previous one. + +module user_settings + #(parameter BASE=0) + (input clk, + input rst, + + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + + output set_stb_user, + output [7:0] set_addr_user, + output [31:0] set_data_user + ); + + wire addr_changed, data_changed; + reg stb_int; + + setting_reg #(.my_addr(BASE+0),.width(8)) sr_0 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(set_addr_user),.changed(addr_changed) ); + + setting_reg #(.my_addr(BASE+1)) sr_1 + (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(set_data_user),.changed(data_changed) ); + + always @(posedge clk) + if (rst|set_stb_user) + stb_int <= 0; + else + if (addr_changed) + stb_int <= 1; + + assign set_stb_user = stb_int & data_changed; + +endmodule // user_settings + |