Merge branch 'fpga_next' into next

1 files changed, 5 insertions, 4 deletions

diff --git a/fpga/usrp2/control_lib/settings_bus_crossclock.v b/fpga/usrp2/control_lib/settings_bus_crossclock.v
index 9c5912042..a61ee8fad 100644
--- a/fpga/usrp2/control_lib/settings_bus_crossclock.v
+++ b/fpga/usrp2/control_lib/settings_bus_crossclock.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -22,16 +22,17 @@
 // the system or dsp clock on the output side
 
 module settings_bus_crossclock
+  #(parameter FLOW_CTRL=0)
   (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
-   input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o);
+   input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked);
 
    wire  full, empty;
    
    fifo_xlnx_16x40_2clk settings_fifo
      (.rst(rst_i),
       .wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
-      .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty));
+      .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty));
 
-   assign set_stb_o = ~empty;
+   assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL);
 
 endmodule // settings_bus_crossclock