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authorJosh Blum <josh@joshknows.com>2010-06-19 01:31:40 +0000
committerJosh Blum <josh@joshknows.com>2010-06-19 01:31:40 +0000
commita9319441d688620e18d5621cc59b98769e670468 (patch)
tree834918c47d69808ca163746788c7a1e0a14462aa /fpga/usrp2/control_lib/setting_reg.v
parent2f9b6d5530df140a5a03120adc98a5ad32a69cc4 (diff)
parent1c1d967ec73906d50ee6e7257a4153db4ab9c507 (diff)
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Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Diffstat (limited to 'fpga/usrp2/control_lib/setting_reg.v')
-rw-r--r--fpga/usrp2/control_lib/setting_reg.v6
1 files changed, 4 insertions, 2 deletions
diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v
index c8aff230f..3d3bb65e5 100644
--- a/fpga/usrp2/control_lib/setting_reg.v
+++ b/fpga/usrp2/control_lib/setting_reg.v
@@ -1,9 +1,11 @@
module setting_reg
- #(parameter my_addr = 0, parameter at_reset=32'd0)
+ #(parameter my_addr = 0,
+ parameter width = 32,
+ parameter at_reset=32'd0)
(input clk, input rst, input strobe, input wire [7:0] addr,
- input wire [31:0] in, output reg [31:0] out, output reg changed);
+ input wire [31:0] in, output reg [width-1:0] out, output reg changed);
always @(posedge clk)
if(rst)