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authorJosh Blum <josh@joshknows.com>2010-04-15 11:24:24 -0700
committerJosh Blum <josh@joshknows.com>2010-04-15 11:24:24 -0700
commit05d77f772317de5d925301aa11bb9a880656dd05 (patch)
tree0910bfb9265fab1644a3d3a1706719f1b038d193 /fpga/usrp2/control_lib/sd_spi_tb.v
parent16818dc98e97b69a028c47e66ebfb16e32565533 (diff)
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moved usrp1 and usrp2 fpga dirs into fpga subdirectory
Diffstat (limited to 'fpga/usrp2/control_lib/sd_spi_tb.v')
-rw-r--r--fpga/usrp2/control_lib/sd_spi_tb.v40
1 files changed, 40 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/sd_spi_tb.v b/fpga/usrp2/control_lib/sd_spi_tb.v
new file mode 100644
index 000000000..e30a5bdf6
--- /dev/null
+++ b/fpga/usrp2/control_lib/sd_spi_tb.v
@@ -0,0 +1,40 @@
+
+
+module sd_spi_tb;
+
+ reg clk = 0;
+ always #5 clk = ~clk;
+ reg rst = 1;
+ initial #32 rst = 0;
+
+ wire sd_clk, sd_mosi, sd_miso;
+ wire [7:0] clk_div = 12;
+ wire [7:0] send_dat = 23;
+ wire [7:0] rcv_dat;
+
+ wire ready;
+ reg go = 0;
+ initial
+ begin
+ repeat (100)
+ @(posedge clk);
+ go <= 1;
+ @(posedge clk);
+ go <= 0;
+ end
+
+ sd_spi dut(.clk(clk),.rst(rst),
+ .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+ .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
+ .go(go),.ready(ready) );
+
+ initial
+ begin
+ $dumpfile("sd_spi_tb.vcd");
+ $dumpvars(0,sd_spi_tb);
+ end
+
+ initial
+ #10000 $finish();
+
+endmodule // sd_spi_tb