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author | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-04-15 11:24:41 -0700 |
commit | 3a196c5d614fbec9b1010b3082245614ba5e0dc9 (patch) | |
tree | 784f075298f5d86c9e7429ce0ff977deaf4315c8 /fpga/usrp2/control_lib/ram_2port.v | |
parent | cbf7a0916f0455743d8446a8edc0f0775e3e63ed (diff) | |
parent | 05d77f772317de5d925301aa11bb9a880656dd05 (diff) | |
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Merge branch 'udp'
Diffstat (limited to 'fpga/usrp2/control_lib/ram_2port.v')
-rw-r--r-- | fpga/usrp2/control_lib/ram_2port.v | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/fpga/usrp2/control_lib/ram_2port.v b/fpga/usrp2/control_lib/ram_2port.v new file mode 100644 index 000000000..3716a7c8a --- /dev/null +++ b/fpga/usrp2/control_lib/ram_2port.v @@ -0,0 +1,42 @@ + + +module ram_2port + #(parameter DWIDTH=32, + parameter AWIDTH=9) + (input clka, + input ena, + input wea, + input [AWIDTH-1:0] addra, + input [DWIDTH-1:0] dia, + output reg [DWIDTH-1:0] doa, + + input clkb, + input enb, + input web, + input [AWIDTH-1:0] addrb, + input [DWIDTH-1:0] dib, + output reg [DWIDTH-1:0] dob); + + reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0]; + integer i; + initial + for(i=0;i<(1<<AWIDTH);i=i+1) + ram[i] <= {DWIDTH{1'b0}}; + + always @(posedge clka) begin + if (ena) + begin + if (wea) + ram[addra] <= dia; + doa <= ram[addra]; + end + end + always @(posedge clkb) begin + if (enb) + begin + if (web) + ram[addrb] <= dib; + dob <= ram[addrb]; + end + end +endmodule // ram_2port |