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| author | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-06-19 01:31:40 +0000 |
| commit | a9319441d688620e18d5621cc59b98769e670468 (patch) | |
| tree | 834918c47d69808ca163746788c7a1e0a14462aa /fpga/usrp2/control_lib/newfifo/fifo_spec.txt | |
| parent | 2f9b6d5530df140a5a03120adc98a5ad32a69cc4 (diff) | |
| parent | 1c1d967ec73906d50ee6e7257a4153db4ab9c507 (diff) | |
| download | uhd-a9319441d688620e18d5621cc59b98769e670468.tar.gz uhd-a9319441d688620e18d5621cc59b98769e670468.tar.bz2 uhd-a9319441d688620e18d5621cc59b98769e670468.zip | |
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Diffstat (limited to 'fpga/usrp2/control_lib/newfifo/fifo_spec.txt')
| -rw-r--r-- | fpga/usrp2/control_lib/newfifo/fifo_spec.txt | 36 |
1 files changed, 0 insertions, 36 deletions
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_spec.txt b/fpga/usrp2/control_lib/newfifo/fifo_spec.txt deleted file mode 100644 index 133b9fa8e..000000000 --- a/fpga/usrp2/control_lib/newfifo/fifo_spec.txt +++ /dev/null @@ -1,36 +0,0 @@ - - -FIFO and Buffer Interface Spec - -Buffer Interface Data Wires -- matches fifo36 - DATA[31:0] - FLAGS[3:0] - Bit 0 SOP - Bit 1 EOP - If SOP=1 && EOP=1, OCC contains error flags - Bits 3:2 OCC[1:0] --> 00 = all 4 bytes - 01 = 1 byte - 10 = 2 bytes - 11 = 3 bytes - -fifo36 --> {OCC[1:0],EOP,SOP,DATA[31:0]} - OCC same as buffer interface - -fifo19 --> {OCC,EOP,SOP,DATA[15:0]} - Doesn't fit well into BRAM, dist RAM ok - OCC = 1 means last word is half full - = 0 means last word is full - -fifo18 --> {EOP,SOP,DATA[15:0]} - No half-word capability? Should we drop sop instead? - -Control Wires - Data into FIFO - SRC_RDY_i Upstream has data for me - DST_RDY_o I have space - Transfer occurs if SRC_RDI_i && DST_RDY_o - -Control Wires - Data out of FIFO - SRC_RDY_o I have data for downstream - DST_RDY_i Downstream has space - Transfer occurs if SRC_RDI_o && DST_RDY_i - |