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author | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2010-06-15 18:24:33 -0700 |
commit | edcc2df10ba59ed91ac9513c2dc1d36e155caaec (patch) | |
tree | 1a1ec2c0b5500990c991c27af03dbe48c10ce7ca /fpga/usrp2/control_lib/newfifo/fifo_cascade.v | |
parent | a89d684ba2b81c6e18d348965dffb919edb56fea (diff) | |
parent | 9445315e6a5cdfb29c4ead73b0fcd4d5fd75b900 (diff) | |
download | uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.gz uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.tar.bz2 uhd-edcc2df10ba59ed91ac9513c2dc1d36e155caaec.zip |
Merge branch 'master' of ettus.sourcerepo.com:ettus/fpga into uhd_master
Conflicts:
fpga/.gitignore
Diffstat (limited to 'fpga/usrp2/control_lib/newfifo/fifo_cascade.v')
-rw-r--r-- | fpga/usrp2/control_lib/newfifo/fifo_cascade.v | 52 |
1 files changed, 0 insertions, 52 deletions
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_cascade.v b/fpga/usrp2/control_lib/newfifo/fifo_cascade.v deleted file mode 100644 index fdd8449bc..000000000 --- a/fpga/usrp2/control_lib/newfifo/fifo_cascade.v +++ /dev/null @@ -1,52 +0,0 @@ - - -// This FIFO exists to provide an intermediate point for the data on its -// long trek from one RAM (in the buffer pool) to another (in the longfifo) -// The shortfifo is more flexible in its placement since it is based on -// distributed RAM - -// This one has the shortfifo on both the in and out sides. -module fifo_cascade - #(parameter WIDTH=32, SIZE=9) - (input clk, input reset, input clear, - input [WIDTH-1:0] datain, - input src_rdy_i, - output dst_rdy_o, - output [WIDTH-1:0] dataout, - output src_rdy_o, - input dst_rdy_i, - output [15:0] space, - output [15:0] occupied); - - wire [WIDTH-1:0] data_int, data_int2; - wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2; - - wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; - wire [15:0] l_space, l_occupied; - - fifo_short #(.WIDTH(WIDTH)) head_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1), - .space(s1_space),.occupied(s1_occupied) ); - - fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1), - .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2), - .space(l_space),.occupied(l_occupied) ); - - fifo_short #(.WIDTH(WIDTH)) tail_fifo - (.clk(clk),.reset(reset),.clear(clear), - .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2), - .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), - .space(s2_space),.occupied(s2_occupied) ); - - assign space = {11'b0,s1_space} + {11'b0,s2_space} + l_space; - assign occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied; - -endmodule // cascadefifo2 - - - - |