Merge FPGA repository back into UHD repository

The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>

1 files changed, 182 insertions, 0 deletions

diff --git a/fpga/usrp2/control_lib/dcache.v b/fpga/usrp2/control_lib/dcache.v
new file mode 100644
index 000000000..384c5a149
--- /dev/null
+++ b/fpga/usrp2/control_lib/dcache.v
@@ -0,0 +1,182 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+
+module dcache
+  #(parameter AWIDTH=14,
+    parameter CWIDTH=6)
+    (input wb_clk_i,
+     input wb_rst_i,
+     
+     input [AWIDTH-1:0] dwb_adr_i,
+     input dwb_stb_i,
+     input dwb_we_i,
+     input [3:0] dwb_sel_i,
+     input [31:0] dwb_dat_i,
+     output [31:0] dwb_dat_o,
+     output dwb_ack_o,
+     
+     input [31:0] dram_dat_i,
+     output [31:0] dram_dat_o,
+     output [AWIDTH-1:0] dram_adr_o,
+     output dram_we_o,
+     output dram_en_o,
+     output [3:0] dram_sel_o );
+
+   localparam TAGWIDTH = AWIDTH-CWIDTH-2;
+   reg 	      stb_d1, ack_d1, miss_d1;
+   reg [AWIDTH-1:0] held_addr;
+   reg [31:0] 	    ddata [0:(1<<CWIDTH)-1];
+   reg [TAGWIDTH-1:0] dtags [0:(1<<CWIDTH)-1];
+   reg 		      dvalid [0:(1<<CWIDTH)-1];
+   
+   wire [CWIDTH-1:0]  rd_line, wr_line;
+   wire [TAGWIDTH-1:0] wr_tags;
+   wire 	       cache_write, invalidate;
+   wire [31:0] 	       wr_data;
+   
+   // /////////////////////////////////////
+   // Write into cache
+   integer 	      i;
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       for(i=0;i<(1<<CWIDTH);i=i+1)
+	 dvalid[i] <= 0;
+     else
+       if(invalidate)
+	 dvalid[wr_line] <= 1'b0;
+       else if(cache_write)
+	 dvalid[wr_line] <= 1'b1;
+   
+   always @(posedge wb_clk_i)
+     if(cache_write)
+       begin
+	  ddata[wr_line] <= wr_data;
+	  dtags[wr_line] <= wr_tags;
+       end
+   
+   // //////////////////////////////////////
+   // Read from Cache
+   wire [TAGWIDTH-1:0] tag_out = dtags[rd_line];
+   wire 	       valid_out = dvalid[rd_line];
+   wire [31:0] 	       data_out	= ddata[rd_line];
+   wire 	       cache_hit = valid_out & (tag_out == dwb_adr_i[AWIDTH-1:CWIDTH+2]);
+   wire 	       cache_miss = ~cache_hit;
+
+   // //////////////////////////////////////
+   // Handle 1-cycle delay of Block-RAM
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= dwb_stb_i;
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       held_addr <= 0;
+     else
+       held_addr <= dwb_adr_i;
+   
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       ack_d1 <= 1'b0;
+     else 
+       ack_d1 <= dwb_ack_o;
+
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       miss_d1 <= 0;
+     else 
+       miss_d1 <= cache_miss;
+
+`define DC_NOCACHE
+//`define DC_BASIC
+//`define DC_FORWARDING_DP
+//`define DC_FORWARDING_SP
+//`define DC_PREFETCH
+
+`ifdef DC_NOCACHE
+   assign 	       dwb_dat_o = dram_dat_i;
+   assign 	       dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = dwb_stb_i;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = 0;
+   assign 	       wr_line = 0;
+   assign 	       wr_tags = 0;
+   assign 	       wr_data = 0;
+   assign 	       cache_write = 0;
+   assign 	       invalidate = 0; 	       
+`endif
+   
+`ifdef DC_BASIC    // Very basic, no forwarding, 2 wait states on miss
+   assign 	       dwb_dat_o = data_out;
+   assign 	       dwb_ack_o = dwb_stb_i & cache_hit;
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = dwb_stb_i;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = dwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = rd_line;
+   assign 	       wr_tags = dwb_adr_i[AWIDTH-1:CWIDTH+2];
+   assign 	       wr_data = dwb_we_i ? dwb_dat_i : dram_dat_i;
+   assign 	       cache_write = dwb_stb_i & (dwb_we_i | (stb_d1 & miss_d1));
+   assign 	       invalidate = dwb_we_i & ~(&dwb_sel_i);
+`endif
+   
+`ifdef DC_FORWARDING_DP   // Simple forwarding, 1 wait state on miss, dual-port ram
+   assign 	       dwb_dat_o = cache_hit ? data_out : dram_dat_i;
+   assign 	       dwb_ack_o = dwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = 1'b1;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = dwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = held_addr[CWIDTH+1:2];
+   assign 	       wr_tags = held_addr[AWIDTH-1:CWIDTH+2];	       
+   assign 	       wr_data = dram_dat_i;
+   assign 	       cache_write = dwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
+   assign 	       invalidate = 0; 	       
+`endif
+
+`ifdef DC_FORWARDING_SP   // Simple forwarding, 1 wait state on miss, single-port ram
+   assign 	       dwb_dat_o = cache_hit ? data_out : dram_dat_i;
+   assign 	       dwb_ack_o = dwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = 1'b1;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = dwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = rd_line;
+   assign 	       wr_tags = dwb_adr_i[AWIDTH-1:CWIDTH+2];
+   assign 	       wr_data = dram_dat_i;
+   assign 	       cache_write = dwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
+   assign 	       invalidate = 0; 	       
+`endif
+
+`ifdef DC_PREFETCH   // Forwarding plus prefetch
+
+`endif
+   
+   
+endmodule // dcache
+