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authorJosh Blum <josh@joshknows.com>2011-05-16 11:58:03 -0700
committerJosh Blum <josh@joshknows.com>2011-05-16 11:58:03 -0700
commit13be023531fa1be8d43b999c3ea5ab477f101fdc (patch)
tree9a24a949aa0d30b9a992d89c232ae1b812b3c09f /fpga/usrp2/control_lib/atr_controller.v
parente6e010e02a12359a31e70ac7fe2ae7c39fa3e9d6 (diff)
parentc8565df0e51922443426a0392f5f1fb4e3743ce1 (diff)
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Merge branch 'use_vita_length' into next
Diffstat (limited to 'fpga/usrp2/control_lib/atr_controller.v')
-rw-r--r--fpga/usrp2/control_lib/atr_controller.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v
index fed2791f9..a161b5e00 100644
--- a/fpga/usrp2/control_lib/atr_controller.v
+++ b/fpga/usrp2/control_lib/atr_controller.v
@@ -7,7 +7,7 @@ module atr_controller
(input clk_i, input rst_i,
input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
input we_i, input stb_i, input cyc_i, output reg ack_o,
- input run_rx, input run_tx, input [31:0] master_time,
+ input run_rx, input run_tx,
output [31:0] ctrl_lines);
reg [3:0] state;